• Posted on: Aug 18, 2025
  • Location: Mountain View, CA
  • Job ID: e4032b32
  • Type: Full Time
  • Posted on: Aug 18, 2025
  • Location: Mountain View, CA
  • Job ID: e4032b32
  • Type: Full Time

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Senior Hardware Architect / RTL Design Engineer

We’re searching for an experienced hardware engineer who thrives at the intersection of architecture, RTL, and verification. The right candidate will bring both hands-on technical expertise and the ability to guide teams through complex design cycles that push the limits of modern silicon.

What You’ll Work On

  • Own the architecture and RTL development of advanced hardware blocks, ensuring successful integration into large-scale systems.

  • Drive verification strategies for highly complex modules, collaborating closely with verification engineers and system architects.

  • Contribute to end-to-end chip design workflows, from early architecture definition to final tapeout.

  • Partner with cross-functional teams to refine specifications and validate hardware/software interfaces.

  • Share knowledge and mentor peers, helping grow technical depth across the team.

  • Explore and apply modern ML techniques in the context of chip design automation and optimization.

What You Bring

  • 5+ years of experience working in chip design environments, ideally with contributions to production tapeouts.

  • Demonstrated expertise developing architectures and RTL for sophisticated IP or subsystems.

  • Background in cutting-edge chip organizations (CPUs, GPUs, SoCs, or leading EDA teams).

  • Proven leadership in technical or team-building capacities.

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related discipline.

Technical Expertise

  • Strong proficiency in SystemVerilog/Verilog and modern SoC design methodologies.

  • Hands-on programming skills in Python for design automation or tooling.

  • Familiarity with verification methodologies (UVM highly valued).

  • Experience developing IP in areas like PCIe5, PHY, LPDDR, memory controllers, NoCs, CPU subsystems, or similar domains.

  • Understanding of hardware/software co-design principles.

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