Micro Architect / Sr. ASIC Design Engineer

MICRO ARCHITECT/Sr. ASIC DESIGN ENGINEER

POSITION DESCRIPTION SUMMARY

Our client is looking for an exceptional Micro architect/ASIC Design Engineer for a complex digital SoC project development. The Engineer will work in a team-oriented environment to collaborate with architecture team to create micro-architecture specification, detailed power, timing and area efficient RTL design and then verify the design through simulation verification. This candidate will be expected to lead a small team to accomplish the goals in a timely manner.

RESPONSIBILITIES

• Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and IP for inclusion in subsystem designs.
• Participate in the development of Architecture and Microarchitecture specifications for the Logic components.
• Provide IP integration support to Subsystem customers and represents RTL team.
• Implement RTL in System Verilog, validating the design, synthesizing the design and closing timing.
• Provide support to design verification team for debug and physical design team for timing closure.
• Work with specifications at multiple levels, including the HAS and MAS (microarchitecture spec).
• Balance design trade-offs with modularity, scalability, DFX requirements, power, area, and performance.

QUALIFICATIONS / EXPERIENCE

The candidate must have a Bachelor’s degree in Electrical/Computer Engineering or Computer Science and 7+ years of experience in: – OR – a Master’s degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience in: – OR – a PhD in Electrical/Computer Engineering or Computer Science and 3+ year of experience in:

• Logic design using System Verilog
• Micro-architecture trade-offs and documentation
• Low-power design using UPF and clock gating
• Multiple clock domain design
• State machine design
• Simulation and debug experience using VCS/Verdi
• Synthesis and speed path debug
• Pre-silicon and post-silicon validation
• Experience with memory coherency design