Seeking a Sr. FPGA Firmware Engineer to join our Engineering team.
This position requires the employee to work mostly onsite – with flexibility or hybrid schedule 2 days work from home per week. We also work a 9/80 schedule, which allows us to be off every other Friday.
The engineer will participate in FPGA firmware development activities. It will support digital design / FPGA design & verification. The position supports new product development and sustainment current product lines, which include avionics Surveillance, Recorders and Display products. The position will support technical leadership in decision-making process for the product, enabling the team to make decisions in a rapid and successful manner. The engineer is responsible for engaging other engineering participants with discipline specific backgrounds to resolve issues and provide a unified engineering response. The individual will provide expertise in technical, schedule and cost targets.
FPGA design and verification
Device migration across FPGA manufacturers
Generation of schematics and review of PWA designs
Generation of requirements, FPGA coding in various industry tools, FPGA verification and traceability mapping
Work within established FPGA processes and checklists, which are consistent and
Support estimation activities associated with new and remapping FPGA design efforts.
Lead Root Cause Failure Investigations of digital designs
Responsible for performing job duties consistent with the company’s Ethics, Financial, Health and Safety Standards.
Experience working in a Continuous Improvement Culture
Ability to work in a teaming environment, while possessing good interpersonal and communications skills
Self-motivated to identify performance issues and provide potential solutions through strong organizational, analytical and problem-solving skills.
Experience designing or troubleshooting high reliability electronics.
Good understanding of product development lifecycle processes
Experience with test equipment and tools including multimeter, oscilloscopes, logic analyzer.
Hands-on, “roll-up-the-sleeves” approach.
Bachelor’s Degree and minimum 6 years of prior relevant experience.
Graduate Degree and a minimum of 4 years of prior related experience.
Preferred Additional Skills:
Architecting, implementing high throughput digital cores / algorithms targeting SOC class FPGAs with interfaces – Ethernet (UDP, TCP/IP), AXI, PCIe/NVMe, USB